Low Power CMOS Digitally Controlled Oscillator

Here, two new designs of CMOS digitally controlled oscillators (DCO) for low power application have been proposed. First design has been implemented with one driving strength controlled delay cell and with two NAND gates used as inverters. The second design with one delay cell and by two NOR gates is presented. The proposed circuits have been simulated in spice with 0.35 μm (micrometer) technology at supply voltage of 3.3V. The first design shows 35-40% reduction in power consumption and second design shows 37.5-41.8% power saving as compared to conventional DCO. The frequency range of first and second design varies [3.1316 3.1085] GHz and [3.8112 – 3.7867] GHz respectively with the variation in control word from ‘000000’ to ‘000001'. Power consumption of first and second design varies [640.3845 700.2977] μW and [617.6616 -6 77.3996] μW respectively.